M58PR256LE datasheet(99/119 Pages) STMICROELECTRONICS

99 / 119 page

M58PR256LE, M58PR512LE, M58PR001LE

Common Flash interface

99/119

(P+32)h = 13Ch

03h

Bank region 1 (Erase block type 1): Page mode and Synchronous mode

capabilities

Bit 0: page-mode reads permitted

Bit 1: synchronous reads permitted

Bit 2: synchronous writes permitted

Bits 3-7: reserved

(P+33)h = 13Dh

0Ah

Bank region 1 (Erase block type 1) programming region information

Bit 0-7: aligned size of programming region in bytes

Bit 8-14: reserved

Bit 15: Legacy Flash operation (ignore bit 0-7)

Bit 16-23: Control mode valid size in bytes

Bit 24-31: reserved

Bit 32-39: Control mode invalid size in bytes

Bit 40-46: reserved

Bit 47: Legacy Flash operation (ignore bit 16-23 and 32-39)

(P+34)h = 13Eh

00h

(P+35)h = 13Fh

10h

(P+36)h = 140h

00h

(P+37)h = 141h

10h

(P+38)h = 142h

00h

The variable P is a pointer which is defined at CFI offset 015h.

Bank regions. There is one bank region, see tables 36, 37, 38, 39, 40 and 41 in Appendix A.

Applies to M58PR256LE.

Applies to M58PR512LE.

Applies to M58PR001LE.

Table 51.

Extended Flash array bank and erase block region information

Offset (1)

The variable P is a pointer which is defined at CFI offset 015h.

Data

Description

(P+39)h = 143h

01h

Number of bank regions within the device(2)

Bank regions. There is one EFA bank region.

Table 50.

Bank and erase block region 1 information(1) (continued)

Offset

Data

Description

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