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SC4517AEVB Arkusz danych(PDF) 10 Page - Semtech Corporation |
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SC4517AEVB Arkusz danych(HTML) 10 Page - Semtech Corporation |
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10 / 15 page ![]() 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC4517A 10 Application Information (Cont.) Thermal Considerations There are three major power dissipation sources for the SC4517A. The internal switch conduction loss, its switching loss due to the high frequency switching actions and the base drive boost circuit loss. These losses can be estimated as: ) V ( D I 500 10 V I 10 5 . 22 D R I P boost o I o 3 on 2 o total ⋅ ⋅ ⋅ + ⋅ ⋅ ⋅ + ⋅ ⋅ = − Where: I O = load current; R ON = on-equivalent resistance of the switch; V BOOST = input voltage or output based on the boost circuit connection. The junction temperature of the SC4517A can be further decided by: total JA A J P T T ⋅ θ + = θ JA is the thermal resistance from junction to ambient. Its value is a function of the IC package, the application layout and the air cooling system. It is recommended that a big copper area attached to Pin 4 or the thermal pad be used for better cooling condition. The freewheeling diode also contributes a significant portion of the total converter loss. This loss should be minimized to increase the converter efficiency by using Schottky diodes with low forward drop (V F). ) D 1 ( I V P o F diode − ⋅ ⋅ = Loop Compensation Design The SC4517A has an internal error amplifier and requires a compensation network to connect between the COMP pin and GND pin as shown in Figure 3. The compensation network includes C4, C5 and R3. R1 and R2 are used to program the output voltage according to: ) R R 1 ( 2 . 1 V 2 1 O + • = Assuming the power stage ESR (equivalent series resistance) zero is an order of magnitude higher than the closed loop bandwidth, which is typically one tenth of the switching frequency, the power stage control to output transfer function with the current loop closed (Ridley model) for the SC4517A will be as follows: C R 1 s 1 R 5 . 2 ) s ( G L L VD ⋅ + ⋅ = Where: R L – Load and C – Output capacitor. The goal of the compensation design is to shape the loop to have a high DC gain, high bandwidth, enough phase margin, and high attenuation for high frequency noises. Figure 3 gives a typical compensation network which offers 2 poles and 1 zero to the power stage: SC4517 IN 2 SW 3 EN 5 FB 6 COMP 7 SYNC 8 R2 R1 R3 C4 C D2 L1 C5 Vout Figure 3. Compensation network provides 2 poles and 1 zero. The compensation network gives the following characteristics: 2 1 2 m 2 P Z 1 COMP R R R g ) s 1 ( s s 1 ) s ( G + ⋅ ⋅ ω + ⋅ ω + ⋅ ω = Where: 5 4 1 C C 1 + = ω 4 3 Z C R 1 ⋅ = ω 5 4 3 5 4 2 P C C R C C ⋅ ⋅ + = ω |
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