SC473 datasheet(11/18 Pages) SEMTECH

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SC473

POWER MANAGEMENT

Start-Up and Soft-Off Sequences:

For the SC473 cold start-up, V5 must rise above its under-

voltage lockout (UVLO) threshold (4.4V typ.) The EN signal

may go high either before UVLO or after (preferred). The

DAC drives 120μA (typical) into the soft-start capacitor on

the SS pin. The SS pin and DAC rise slowly until the VID(4:0)

When the voltage hits the lower PWRGD threshold, PWRGD

goes high, and start-up is complete.

In a normal shutdown, the EN signal is driven low, the TG

and BG signals are driven low, tri-stating the power chains.

An approximately 10

Ω FET on the FB+ signal discharges

Vcore slowly and prevents normal amounts of leakage from

pulling Vcore high. The DAC is discharged to zero, but the

power regulation circuitry is inactive, and PWRGD is low.

DAC Description:

A +/-0.85% 5-bit digital-to-analog converter (DAC) serves as

the programmable reference source of the Core Compara-

tor. Programming is accomplished by logic voltage levels

applied to the DAC inputs. The VID code vs. the DAC output

is shown in Table 1. The ﬁve voltage identiﬁcation pins are

used to support automatic selection of V

OUT voltages.

DAC Slew Rate Control:

The DAC also has integrated slew-rate control with to

charge and discharge the soft-start capacitor. All operat-

ing voltage transitions including soft-start use the 120μA

source to charge the soft-start capacitor.

Power Supply Protection:

The UVLO circuit consists of a comparator that monitors

the input supply voltage level, V5. The SC473 is in UVLO

mode when its supply voltage has not ramped above the

upper threshold or dropped below the lower threshold. The

output of the UVLO comparator turns on or off the internal

bias, enables or disables the SC473 output, and initiates

or resets the soft-start timer.

The OVP circuit of SC473 monitors the processor core V

OUT

voltage for an over-voltage condition. If the FB voltage is

200mV greater than the DAC voltage (i.e., out of the pow-

ergood window), the SC473 will latch off and hold the low-

side driver on permanently. Either the power or EN must

be recycled to clear the latch. The latch is disabled

Applications Information (Cont.)

during soft-start and VID/DeeperSleep transitions. For

safety, the latch is enabled if the FB voltage exceeds 1.7V

even during VID transitions.

The device will be disabled and latched off when the

internal junction temperature reaches approximately

160°C. Either the power or EN must be recycled to clear

the latch.

Power Monitor:

The SC473 adds a power monitor feature to accurately

predict the graphics CPU power consumption. The power

monitor output depends on the current sensing methodol-

ogy used. The following diagram and equation predict the

ideal PMON output.

Similar exercise can be done for R-SENSE conﬁguration

as shown below:

Power Monitor Implementation for SC473 (DCR Sense)

R33

+Vcc_core

R27

16.2k

R24

18.2k

TH2

33k

R30

R28

RDCR

C54

DRN

I LOAD

IR33

DC Voltage Between Two Terminals is:

VDCR = I LOAD x RDCR

Voltage

Between these

two terminals is

Veq

Req = Parallel

Combination of Resistors

shown in the box

VR33

CS+

CS-

28.5

Vcc_core

R33

PMON_Ideal

R33

IR33

VR33

R33)

R30

(R28

Veq

IR33

R27)

(Req

Req)

(VDCR

Veq

R33)

R30

R28

R24

(TH2

R33)

R30

R24)(R28

(TH2

Req

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