[AK4344]

SYSTEM DESIGN

Figure 19 and Figure 20 shows the system connection diagram. The evaluation board is available which demonstrates

application circuits, the optimum layout, power supply arrangements and measurement results.

MCLK

1

BICK

2

SDTI

3

LRCK

4

PDN

5

CSN

6

CCLK

7

CDTI

8

TEST2

16

CDTO

15

VDD

14

VSS

13

VCOM

12

LOUT

11

ROUT

10

TEST1

9

Master Clock

AK4344

fs

24bit Audio Data

Reset & Power down

64fs

4.7u

0.1u

+

Rch Out

Lch Out

Analog Ground

Digital Ground

Analog Supply

2.7 to 3.6V

+

10u

Micro

Controller

Figure 19. Typical Connection Diagram (Mode bit = “0”, 4 wire mode )

MCLK

1

BICK

2

SDTI

3

LRCK

4

PDN

5

CSN

6

CCLK

7

CDTI

8

TEST2

16

SDTI2

15

VDD

14

VSS

13

VCOM

12

LOUT

11

ROUT

10

TEST1

9

Master Clock

AK4344

fs

24bit Audio Data1

Reset & Power down

64fs

4.7u

0.1u

+

Rch Out

Lch Out

Analog Ground

Digital Ground

Analog Supply

2.7 to 3.6V

+

10u

Micro

Controller

24bit Audio Data2

Figure 20. Typical Connection Diagram (Mode bit = “1”, 3 wire mode )

MS0641-E-00

2007/06

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