ISD5216P datasheet(13/75 Pages) WINBOND

13 / 75 page

ISD5216

Publication Release Date: Jan. 31, 2006

- 13 -

Revision B.4

7.2.2. Digital Input to Analog Output Path

The digital input interface must be selected to either PCM or I

2S using the interface selector bit (I2S0)

in the configuration register. The compression format must also be selected with bits (LAW1 – LAW0)

in the configuration registers.

The external clock input signal on pin MCLK and the internal clock dividers must be set to values

supporting the selected digital input signal.

The digital smoothing and interpolation filter runs at 3.4 kHz and feeds the

ΣΔ D/A converter that can

be switched off to conserve power and reduce noise using the D/A power down bit (DAPD).

The analog output amplifier gain is controlled from configuration registers bits (COG2 – COG0) from -

8 dB to +6 dB.

7.2.3. CODEC External Clock Configuration

The ISD5216 has two Master Clock configuration bits that allow four possible Master Clock

frequencies. Bits CKD2 and CKDV set the Master Clock Division ratios. These are bits D12 and D8 of

CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also set the

CODEC sample frequency as shown in the following table.

Master Clock Possible Settings

FMCLK

HSR0 (D5)

(CFG2)

CKD2 (D12)

(CFG2)

CKDV (D8)

(CFG2)

FSCODEC

13.824 MHz

8 kHz

20.48 MHz

11.852 kHz*

27.648 MHz

8 kHz

40.96 MHz

11.852 kHz*

13.824 MHz

32 kHz*

20.48 MHz

44.1 - 48 kHz

27.648 MHz

32 kHz*

40.96 MHz

44.1-48 kHz

*not tested

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