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RT9703GS Arkusz danych(PDF) 13 Page - Richtek Technology Corporation |
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RT9703GS Arkusz danych(HTML) 13 Page - Richtek Technology Corporation |
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13 / 14 page ![]() RT9703 13 DS9703-08 March 2007 www.richtek.com Fault Flag Filtering (Optional) The transient inrush current to downstream capacitance may cause a short-duration error flag, which may cause erroneous over-current reporting. A simple 1ms RC low- pass filter (10k Ω and 0.1μF) in the flag line eliminates short-duration transients. PCB Layout In order to meet the voltage drop, droop, and EMI requirements, careful PCB layout is necessary. The following guidelines must be considered: Keep all input and output traces as short as possible and use at least 150-mil & 2 ounce copper for all races. Avoid vias as much as possible. If vias are necessary, make them as large as feasible. Place a ground plane under all circuitry to lower both resistance and inductance and improve DC and transient performance (Use a separate ground and power plans if possible). Locate the bypass capacitors as close as possible to the input and output pin of the RT9703. GND VOUT EN VIN IP FLG GND GND Board Layout |
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