LPC2131_32_34_36_38_4

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 04 — 16 October 2007

12 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input

function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.

[3]

functionality.

[4]

5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured

for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital

section of the pad is disabled.

[5]

5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When

configured as the DAC output, digital section of the pad is disabled.

[6]

5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 k

Ω to 300 kΩ.

[7]

5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

[8]

Pad provides special analog functionality.

P1.24/

TRACECLK

32[6]

O

TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

P1.25/EXTIN0

28[6]

I

EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.

P1.26/RTCK

24[6]

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up. LOW on RTCK while RESET is LOW

enables pins P1.31:26 to operate as Debug port after reset.

P1.27/TDO

64[6]

O

TDO — Test Data out for JTAG interface.

P1.28/TDI

60[6]

I

TDI — Test Data in for JTAG interface.

P1.29/TCK

56[6]

I

TCK — Test Clock for JTAG interface.

P1.30/TMS

52[6]

I

TMS — Test Mode Select for JTAG interface.

P1.31/TRST

20[6]

I

TRST — Test Reset for JTAG interface.

RESET

57[7]

I

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

62[8]

I

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

61[8]

O

Output from the oscillator amplifier.

RTCX1

3[8]

I

Input to the RTC oscillator circuit.

RTCX2

5[8]

O

Output from the RTC oscillator circuit.

6, 18, 25, 42,

50

I

Ground: 0 V reference.

59

I

Analog ground: 0 V reference. This should nominally be the same voltage

23, 43, 51

I

3.3 V power supply: This is the power supply voltage for the core and I/O

ports.

7I

Analog 3.3 V power supply: This should be nominally the same voltage as

to power the on-chip PLL.

VREF

63

I

should be isolated to minimize noise and error. Level on this pin is used as a

reference for A/D and D/A convertor(s).

VBAT

49

I

RTC power supply: 3.3 V on this pin supplies the power to the RTC.

Table 3.

Symbol

Pin

Type

Description