ST72682 datasheet(29/36 Pages) STMICROELECTRONICS

29 / 36 page

ST72682

Electrical characteristics

29/36

7.8

Control pin characteristics

7.8.1

Asynchronous RESET pin

TA ranges between 0 and +55 °C unless otherwise specified.

Figure 17.

Typical RON on RESET pin

Table 22.

Asynchronous RESET pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(1)

The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1.

Otherwise the reset will not be taken into account internally.

0.16VDD33

VIH

Input high level voltage

0.85VDD33

Vhys

Schmitt trigger voltage

hysteresis(1)

450

RON

Pull-up equivalent resistor

VDD33 = 3.3 V

Ω

VDD33 = 2 V

100

teh(RSTL) External reset pulse hold time

(2)

To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short

pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production,

guaranteed by design.

2.5

µs

tg(RSTL) Filtered glitch duration

(3)

The reset network protects the device against parasitic resets.

200

tew(RSTL) External reset pulse duration

(4)

The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator

at power-up. Not tested in production, guaranteed by design.

500

µs

tiw(RSTL) Internal reset pulse duration

Tcpu

NRESET pull-up (kOhms)

100

VDD (V)

ST72682 Arkusz danych(PDF) 29 Page - STMicroelectronics

ST72682 Arkusz danych(HTML) 29 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Arkusz danych Pobierz

Link URL