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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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DF6811 Arkusz danych(PDF) 2 Page - Digital Core Design |
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DF6811 Arkusz danych(HTML) 2 Page - Digital Core Design |
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2 / 9 page  All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ● Fully synthesizable, static synchronous design with no internal tri-states ● No internal reset generator or gated clock ● Scan test ready ● Technology independent HDL source code ● Core can be fully customized ● 1 GHz virtual clock frequency compared to original implementation DESIGN FEATURES ♦ ONE GLOBAL SYSTEM CLOCK ♦ SYNCHRONOUS RESET The DF6811 has 3 reset vectors sources, which easy identify a cause of system reset. ♦ ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE DATA MEMORY: The DF6811 can address up to 16M bytes of Data Memory via the function in- terconnect signals. The 256 bytes of Data Memory in every 64k page is reserved for the Function Registers. Extra DPP (Data Page Pointer) register is used for segments swapping. Data Memory can be imple- mented as synchronous or asynchronous RAM. SYSTEM FUNCTION REGISTERS: Up to 256 System Function Regis- ters(SFRs) may be implemented to the DF6811 design. SFRs are memory mapped into Data Memory within any 4k bytes address space . PROGRAM MEMORY: Up to 64kB of Program Memory may be implemented to the DF6811 design. Pro- gram Memory can be implemented as syn- chronous or asynchronous ROM. PERIPHERALS The peripherals listed below are implemented in standard configuration of DF6811. ● DoCDTM on Chip Debugger ○ Processor execution control ○ Read, write all processor contents ○ Hardware execution breakpoints ○ Three wire communication interface ● Four 8-bit I/O Ports ● Interrupt Controller ○ 20 interrupt sources ○ 17 priority levels ○ Dedicated Interrupt vector for each interrupt ● Main16-bit timer/counter system ○ 16 bit free running counter ○ Four stage programmable prescaller ○ Timer clocked by internal source ○ Real Time Interrupt ● 16-bit Compare/Capture Unit ○ Three independent input-capture functions ○ Five output-compare channels ○ Events capturing ○ Pulses and digital signals generation ○ Gated timers ○ Sophisticated comparator ○ Pulse width modulation ○ Pulse width measuring ● 8-bit Pulse accumulator ○ Two major modes of operation ○ Simple event counter ○ Gated time accumulation ○ Clocked by internal source or external pin ● SPI – Master and Slave Serial Peripheral Interface ○ Supports speeds up 1/8 of system clock ○ Software selectable polarity and phase of se- rial clock SCK ○ System errors detection ○ Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) ○ Interrupt generation |
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