LTC3443 datasheet(6/16 Pages) LINER

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LTC3443

sn3443 3443fs

BLOCK DIAGRA

–

PWM

LOGIC

AND

OUTPUT

PHASING

GATE

DRIVERS

AND

ANTICROSS

CONDUCTION

Burst Mode

OPERATION

CONTROL

5µs DELAY

GND

UVLO

2.4V

SLEEP

MODE/SYNC

1 = Burst Mode

OPERATION

0 = FIXED FREQUENCY

600kHz

OSC

SYNC

SUPPLY

CURRENT

LIMIT

SW A

SW1

PVIN

VIN

VCC

INTERNAL

SW2

VIN

2.4V TO 5.5V

SW D

ISENSE

AMP

ERROR

AMP

1.22V

CLAMP

REVERSE

CURRENT

LIMIT

SW B

3.2A

AVERAGE

CURRENT LIMIT

SW C

PGND

–0.4A

PGND

VOUT

SHDN/SS

SHUTDOWN

RSS

VIN

CSS

3443 BD

VOUT

2.4V TO 5.25V

PWM

COMPARATORS

–

100

gm =

THERMAL

SHUTDOWN

÷2

CLAMP

MODE

PI FU CTIO S

MODE/SYNC = Low: Disable Burst Mode operation and

maintain low noise, constant frequency operation .

MODE/SYNC = External CLK : Synchronization of the

internal oscillator and Burst Mode operation disable. A

clock pulse width between 100ns and 2µs and a clock

frequency between 1.38MHz and 2.4MHz (twice the

desired frequency) is required to synchronize the IC.

fOSC = fSYNC/2

VOUT (Pin 8): Output of the Synchronous Rectifier. A filter

capacitor is placed from VOUT to GND. A ceramic bypass

capacitor is recommended as close to the VOUT and GND

pins as possible.

PVIN (Pin 9): Power VIN Supply Pin. A 10µF ceramic capaci-

tor is recommended as close to the PVIN and PGND pins

as possible

VIN (Pin 10): Input Supply Pin. Internal VCC for the IC.

VC (Pin 11): Error Amp Output. A frequency compensation

network is connected from this pin to the FB pin to

compensate the loop. See the section “Compensating the

Feedback Loop” for guidelines.

FB (Pin 12): Feedback Pin. Connect resistor divider tap

here. The output voltage can be adjusted from 2.4V to

5.25V. The feedback reference voltage is typically 1.22V.

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