2

Pinout

CD54HC237 (CERDIP)

CD74HC137 (PDIP, TSSOP)

CD74HCT137 (PDIP, SOIC)

CD74HC237 (PDIP, SOIC, SOP, TSSOP)

CD74HCT237 (PDIP)

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

LE

GND

15

14

13

12

10

7

9

11

1

3

237

137

6

2

4

5

LE

3-BIT

LATCH

1 OF 8

DECODER

GND = 8

HC/HCT HC/HCT

’HC137, ’HCT137 TRUTH TABLE

INPUTS

OUTPUTS

LE

X

X

H

X

X

X

HHHHHHHH

X

L

X

X

X

X

HHHHHHHH

L

H

LLLLL

H

H

H

H

H

H

H

L

H

L

L

L

H

H

L

HHHHHH

L

H

L

L

H

L

HH

L

H

HHHH

L

H

L

L

HHHHH

L

HHHH

L

H

L

H

L

L

HHHH

L

HHH

LHLHLH

H

H

H

H

H

LH

H

L

H

L

H

H

L

HHHHHH

L

H

L

H

L

H

HHHHHHHHH

L

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

’HC237, ’HCT237 TRUTH TABLE

INPUTS

OUTPUTS

LE

X

X

H

X

X

X

LLLLLLLL

X

L

X

X

X

X

LLLLLLLL

L

H

LLLL

H

LLLLLLL

LHL

L

LHLHL

L

L

L

L

L

L

H

LL

H

L

LL

H

L

LLLL

L

H

LL

H

H

LLL

H

LLLL

L

H

L

H

LLLLLL

H

L

LL

LHLHLHL

L

L

L

LHL

L

L

H

L

H

H

L

LLLLLL

H

L

L

H

L

H

H

H

LLLLLLL

H

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237