F2913 Datasheet

© 2017–2023 Renesas Electronics Corporation

12

February 8, 2023

Control Mode

Table 7.

Switch Control Truth Table

C1

C2

RFC – RF1

RFC – RF2

LOW

LOW

OFF

OFF

LOW

HIGH

OFF

ON

HIGH

LOW

ON

OFF

HIGH

HIGH

N/A

N/A

Application Information

Default Start-up

The C1 and C2 control pins include no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH.

Power Supplies

A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to

minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to

fail. Supply voltage change or transients should have a slew rate slower than 1V / 20µs. In addition, all control pins should remain at 0V

(± 0.3V) while the supply voltage ramps up or while it returns to zero.

Control Pin Interface

If a clean control signal for pins 16 and 17 cannot be guaranteed due to overshoot, undershoot, or ringing, etc., the following circuit at the

input of the control pins is recommended.

Figure 27. Control Pin Signal Integrity Improvement Circuit

F2913

GND

1

EP

2

3

4

5

11

12

13

14

15

6

7

8

9 10

20 19 18 17 16

RF1

GND

GND

GND

GND

RF2

GND

GND

GND

GND GND RFC GND GND

VDD GND GND

C1

C2

5 kΩ

2 pF

2 pF

5 kΩ