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Rev C, 4/27/2023

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FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Pixel Control Registers (PXC: [0x0000 – 0x01FF])

The mapping of pixels to the PXC bits that control them is as follows: The 64 rows in the pixel array are numbered consecutively,

from row 00 at the top to row 63 at the bottom. The 64 columns in the pixel array are divided into eight groups of eight

contiguous columns. The column groups are numbered non-consecutively: group 0 contains the leftmost 8 columns, group 4

contains the next-leftmost 8 columns, group 1 contains the next-leftmost 8 columns, then group 5, then group 2, then group 6;

group 3 contains the second-rightmost 8 columns, and group 7 contains the rightmost 8 columns. The address of the PXC register

that controls a particular set of 8 pixels is found by concatenating the row number (6 bits) and the column group number (3 bits)

of the set of pixels, as shown below:

Table 6. PXC Register Address

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

Row #

Col. Group #

A single PXC register controls 8 pixels, with the bits from least-significant to most-significant controlling the pixels in the set

of 8 from left to right: the least-significant bit controls the leftmost pixel of the 8, and the most-significant bit controls the

rightmost pixel of the 8. If the value of the PXC register bit controlling a particular pixel is 1, then the photocurrent of that

pixel does contribute to the aggregated output current to which the column is assigned by its CCFG register. If the value of

the PXC register bit controlling a particular pixel is 0, then the photocurrent of that pixel is shunted to ground and does not

contribute to the aggregated output current to which the column is assigned by its CCFG register.

Table 7. Bits Within a PXC Register

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

Rightmost

pixel

2nd-

rightmost

pixel

3rd-

rightmost

pixel

4th-

rightmost

pixel

4th-

leftmost

pixel

3rd-

leftmost

pixel

2nd-

leftmost

pixel

Leftmost

pixel

Column Configuration Registers (CCFG: [0x0400 – 0x041F])

Each CCFG register controls two adjacent pixel columns: the four least-significant bits control the leftmost of the two

columns, and the four most-significant bits control the rightmost of the two columns. The column pairs controlled by

individual CCFG registers step from left to right with increasing address: [0x0400] controls the leftmost pair of columns,

[0x0401] controls the second-leftmost pair, [0x041E] controls the second-rightmost pair, and [0x041F] controls the

rightmost pair. The value of each nibble in a CCFG register selects the aggregated photocurrent (A+, A-, B+, B-, Z+, Z-) to

which the photocurrents from all “ON” pixels in the corresponding column contribute, according to the table below.

Table 8. CCFG Byte

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

Rightmost column of pair

Leftmost column of pair