6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators

having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

CL

(1)

RL

From Output

Under Test

VCC

Test

Point

S1

S2

(1) CL includes probe and test-fixture capacitance.

Figure 6-1. Load Circuit for 3-State Outputs

50%

Input

50%

VCC

0 V

50%

50%

VOH

VOL

tPLH

(1)

tPHL

(1)

VOH

VOL

tPHL

(1)

tPLH

(1)

Output

Output

50%

50%

(1) The greater between tPLH and tPHL is the same as tpd.

Figure 6-2. Voltage Waveforms, Standard CMOS

Inputs Setup Propagation Delays

50%

Output

Control

50%

VCC

0 V

50%

50%

§ 9CC

VOL

tPZL

(3)

tPLZ

(4)

90%

VOH

§ 0 V

tPZH

(3)

tPHZ

(4)

Output

Waveform 1

S1 at VLOAD

(1)

Output

Waveform 2

S1 at GND

(2)

10%

(1) tPLZ and tPHZ are the same as tdis.

(2) tPZL and tPZH are the same as ten.

Figure 6-3. Voltage Waveforms, Standard CMOS

Inputs Propagation Delays

VOH

VOL

Output

VCC

0 V

Input

tf

(1)

tr

(1)

90%

10%

90%

10%

tr

(1)

90%

10%

tf

(1)

90%

10%

(1) The greater between tr and tf is the same as tt.

Figure 6-4. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Input Devices

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CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1

SCHS382A – JANUARY 2010 – REVISED AUGUST 2022

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