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Zakładka z wyszukiwarką danych komponentów |
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STM32F429NET6XXX Arkusz danych(PDF) 99 Page - STMicroelectronics |
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STM32F429NET6XXX Arkusz danych(HTML) 99 Page - STMicroelectronics |
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99 / 231 page  DocID024030 Rev 6 99/231 STM32F427xx STM32F429xx Electrical characteristics 192 Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 18: Limitations depending on the operating power supply range). • Regulator ON • The voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows: – Scale 3 for fHCLK ≤ 120 MHz – Scale 2 for 120 MHz < fHCLK ≤ 144 MHz – Scale 1 for 144 MHz < fHCLK ≤ 180 MHz. The over-drive is only ON at 180 MHz. • The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. • External clock frequency is 4 MHz and PLL is ON when fHCLK is higher than 25 MHz. • The maximum values are obtained for VDD = 3.6 V and a maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. |
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