POWER-ON RESET (POR)

1.2Vto3.6V

0.9V

0.3V

0V

V

DD

t

VDD_OFF_RAMP

t

VDD_OFF

t

VDD_ON_RAMP

Temperature( C)

°

-40

-20

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0

20

40

60

80

100

RecommendedV

OffTime

forT = 40 Cto+85 C

-

°

°

DD

A

TypicalV

OffTimeforVariousTemperatures

DD

TSC2007

www.ti.com...................................................................................................................................................... SBAS405A – MARCH 2007 – REVISED MARCH 2009

During TSC2007 power-up, an internal power-on reset (POR) is automatically implemented. The POR brings the

TSC to the default working condition, and checks the A0 and A1 pins for the two LSBs of the I2C address. The

TSC2007 senses the power-up curve to decide whether or not to implement a POR.

It is required to follow the power-on/off slope and interval requirements, as provided in the Electrical

Characteristics, in order to ensure a proper POR of the TSC2007.

Figure 35. Power-On Reset Timing

Table 7. Timing Requirements for Figure 35

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

VDD off ramp

TA = –40°C to +85°C

2

kV/s

TA = –40°C to +85°C, VDD = 0V

1.2

s

VDD off time

TA = –20°C to +85°C, VDD = 0V

0.3

s

VDD on ramp

TA = –40°C to +85°C

12

kV/s

Figure 36. VDD Off Time vs Temperature

Copyright © 2007–2009, Texas Instruments Incorporated

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Product Folder Link(s): TSC2007