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TMS320VC33 Arkusz danych(PDF) 30 Page - Texas Instruments

Numer części TMS320VC33
Szczegółowy opis  DIGITAL SIGNAL PROCESSOR
PDF  59 Pages
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Producent  TI2 [Texas Instruments]
Strona internetowa  https://www.ti.com
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TMS320VC33 Arkusz danych(HTML) 30 Page - Texas Instruments

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TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
clock circuit timing (continued)
The following tables define the timing requirements and switching characteristics for EXTCLK.
timing requirements for EXTCLK, all modes (see Figure 17 and Figure 18)
MIN
MAX
UNIT
t
Rise time EXTCLK
F=Fmax, x0.5 and x1 modes
1
ns
tr(EXTCLK)
Rise time, EXTCLK
F<Fmax
4
ns
t
Fall time EXTCLK
F=Fmax, x0.5 and x1 modes
1
ns
tf(EXTCLK)
Fall time, EXTCLK
F<Fmax
4
ns
x5 mode
21
tw(EXTCLKL)
Pulse duration, EXTCLK low
x1 mode
5.5
ns
tw(EXTCLKL)
Pulse duration, EXTCLK low
x0.5 mode
4.0
ns
x5 mode
21
tw(EXTCLKH)
Pulse duration, EXTCLK high
x1 mode
5.5
ns
tw(EXTCLKH)
Pulse duration, EXTCLK high
x0.5 mode
4.0
ns
x5 PLL mode
40
60
tdc(EXTCLK)
Duty cycle, EXTCLK [tw(EXTCLKH) /tc(H)]
x1 and x0.5 modes, F = max
45
55
%
tdc(EXTCLK)
Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)]
x1 and x0.5 modes, F = 0 Hz
0
100
%
x5 mode
83.3
200
Cycle time, EXTCLK, VC33-120
x1 mode
16.7
t
Cycle time, EXTCLK, VC33 120
x0.5 mode
10
ns
tc(EXTCLK)
x5 mode
66.7
200
ns
Cycle time, EXTCLK, VC33-150
x1 mode
13.3
Cycle time, EXTCLK, VC33 150
x0.5 mode
10
x5 mode
5
12
Frequency range, 1/tc(EXTCLK), VC33-120
x1 mode
0
60
F
Frequency range, 1/tc(EXTCLK), VC33 120
x0.5 mode
0
100
MHz
Fext
x5 mode
5
15
MHz
Frequency range, 1/tc(EXTCLK), VC33-150
x1 mode
0
75
Frequency range, 1/tc(EXTCLK), VC33 150
x0.5 mode
0
100
switching characteristics for EXTCLK over recommended operating conditions, all modes
(see Figure 17 and Figure 18)
PARAMETER
MIN
TYP
MAX
UNIT
Vmid
Mid-level, used to measure duty cycle
0.5 * DVDD
V
t
Delay time, EXTCLK to H1 and x1 mode
2
4.5
7
ns
td(EXTCLK-H)
Delay time, EXTCLK to H1 and
H3
x0.5 mode
2
4.5
7
ns
tr(H)
Rise time, H1 and H3
3
ns
tf(H)
Fall time, H1 and H3
3
ns
td(HL-HH)
Delay time, from H1 low to H3 high or from H3 low to H1 high
--1.5
1.5
ns
x5 PLL mode
1/(5 * fext)
tc(H)
Cycle time, H1 and H3
x1 mode
1/fext
ns
tc(H)
Cycle time, H1 and H3
x0.5 mode
2/fext
ns



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