LP8550TLXSLASHNOPB datasheet(22/49 Pages) TI2

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SCL

3 - 6

Start

Condition

Acknowledgment

Signal From Receiver

Data Output

Receiver

Data Output

Transmitter

Transmitter Stays Off the

Bus During the

Acknowledgment Clock

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

LP8550

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

www.ti.com

8.5 Programming

8.5.1 I2C-Compatible Serial Bus Interface

8.5.1.1 Interface Bus Overview

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the ICs connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCLK). These lines

should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the SCLK. The LP8550 is always a slave device.

8.5.1.2

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

SCLK. Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCLK and in the middle of a transaction, aborts the current transaction.

New data should be sent during the low SCLK state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 20. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow as described in

below sections.

Figure 21. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCLK) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCLK is high indicates a Stop Condition.

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