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2

Connection Diagram

Pin Descriptions

Logic Symbols

IEEE/IEC

Truth Table

(Each Half)

H

HIGH Voltage Level

L

LOW Voltage Level

X

Immaterial

 LOW-to-HIGH Clock Transition

Q0 (Q0) Previous Q (Q) before LOW-to-HIGH Transition of Clock

Pin Names

Description

D1, D2

Data Inputs

CP1, CP2

Clock Pulse Inputs

CD1, CD2

Direct Clear Inputs

SD1, SD2

Direct Set Inputs

Q1, Q1, Q2, Q2

Outputs

Inputs

Outputs

SD

CD

CP

D

Q

Q

LH

X

X

H

L

HL

X

X

L

H

LL

X

X

H

H

HH



HH

L

HH



LL

H

HH

L

X

Q0

Q0