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BQ27Z561-R1 Arkusz danych(PDF) 9 Page - Texas Instruments |
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BQ27Z561-R1 Arkusz danych(HTML) 9 Page - Texas Instruments |
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9 / 27 page ![]() 7.20 HDQ Timing (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tTRND Host turn around time Host drives HDQ after device drives HDQ 250 µs tRISE HDQ line rising time to logic 1 1.8 µs tRST HDQ Reset Host drives HDQ low before device reset 2.2 s SCL SDA tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr tBUF Figure 7-1. I2C Timing t(B) t(BR ) t(H W 1) t(H W 0) t(C YC H ) t(D W 1) t(D W 0) t(C YC D ) B reak 7-bit addres s 8-bit data (a) B reak and B reak R ec ov ery (c ) H os t T rans m itted B it (d) G auge T rans m itted B it (e) G auge to Hos t Res pons e 1.2V t(R ISE) (b) H D Q line ris e tim e 1 - b it R / W t(R SPS) t(R ST ) (f) H D Q R es et f. H D Q H o s t to fu e l g a u g e e . F u e l g a u g e to H o s t r e s p o n s e fo r m a t d . F u e l g a u g e to H o s t c o m m u n ic a tio n c . H D Q H o s t to fu e l g a u g e c o m m u n ic a tio n b . R is e tim e o f H D Q lin e a . H D Q B r e a k in g Figure 7-2. HDQ Timing www.ti.com BQ27Z561-R1 SLUSDH5B – MARCH 2019 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: BQ27Z561-R1 |
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