ADCLK

6X ADCLK

SERIAL DATA

1X ADCLK

LCLK

P

LCLK

N

OUT

P

OUT

N

ADCLK

P

ADCLK

N

Sample n data

Input

t

PROP

t

D(A)

Sample n

Sample n + 6

D1 D2 D3 D4 D5 D6 D7

0

0

D0

0

0

D0 D1 D2 D3 D4 D5 D6 D7

D9

D8

1

t

SAMPLE

t

S

2

D9

D8

0

0

6.5 Clock Cycles

NOTE: Serial data bit format shown in LSB first mode.

t

1

t

3

t

5

t

6

t

4

t

7

t

8

t

2

AVDD (3V to 3.6V)

LVDD (3V to 3.6V)

Device Ready

For ADC Operation

Device Ready

For ADC Operation

Device Ready

For Serial Register Write

Start of Clock

AVDD

LVDD

RESET

CS

ADCLK

NOTE: 10

µs < t

1 < 50ms; 10µs < t2 < 50ms; −10ms < t3 < 10ms; t4 > 10ms; t5 > 100ns; t6 > 100ns; t7 > 10ms; and t8 > 100µs.

ADS5277

SBAS333D – FEBRUARY 2005 – REVISED JANUARY 2009............................................................................................................................................ www.ti.com

LVDS TIMING DIAGRAM (Per ADC Channel)

RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING

8

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