ADC3421 datasheet(32/80 Pages) TI2

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Input Clock Duty Cycle (%)

70.3

70.5

70.7

70.9

71.1

71.3

D429

SNR

SFDR

Input Clock Duty Cycle (%)

69.8

70.2

70.4

70.6

70.8

D430

SNR

SFDR

Differential Clock Amplitude (Vpp)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

102

105

D427

SNR

SFDR

Differential Clock Amplitude (Vpp)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

D428

SNR

SFDR

Temperature (°C)

-40

-15

100

D425

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

Temperature (°C)

-40

-15

69.5

69.9

70.3

70.7

71.1

71.5

D426

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

ADC3421, ADC3422, ADC3423, ADC3424

SBAS673A – JULY 2014 – REVISED OCTOBER 2015

www.ti.com

Typical Characteristics: ADC3423 (continued)

Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.

Figure 85. Spurious-Free Dynamic Range vs

Figure 86. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (170 MHz)

Figure 87. Performance vs Clock Amplitude (40 MHz)

Figure 88. Performance vs Clock Amplitude (150 MHz)

Figure 89. Performance vs Clock Duty cycle (30 MHz)

Figure 90. Performance vs Clock Duty Cycle (150 MHz)

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