| Zakładka z wyszukiwarką danych komponentów |
|
TS4871 Arkusz danych(PDF) 24 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TS4871 Arkusz danych(HTML) 24 Page - STMicroelectronics |
|
24 / 42 page ![]() Figure 84. Demoboard top solder layer Figure 85. Demoboard bottom solder layer 5.1 BTL configuration principle The TS4871 is a monolithic power amplifier with a BTL output type. BTL (bridge tied load) means that each end of the load is connected to two single ended output amplifiers. Thus, we have: Single ended output 1 = Vout1 = Vout (V) Single ended output 2 = Vout2 = -Vout (V) And Vout1 - Vout2 = 2Vout (V) The output power is: Pout= 2VoutRMS2 RL W (1) For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single ended configuration. 5.2 Gain In typical application schematic In flat region (no effect of Cin), the output voltage of the first stage is: Vout1= −VinRfeedRin V For the second stage : Vout2 = -Vout1 (V) The differential output voltage is: Vout2−Vout1=2VinRfeedRinV The differential gain named gain (Gv) for more convenient usage is: Gv= Vout2−Vout1 Vin =2RfeedRin Remark : Vout2 is in phase with Vin and Vout1 is 180 phased with Vin. It means that the positive terminal of the loud speaker should be connected to Vout2 and the negative to Vout1. TS4871 Application information DS2547 - Rev 10 page 24/42 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |