We can expect a current of 5 A, an error of 2.9% @ 25 °C.

The error expected in this case is largely better (2.9%), than the worst-case calculation (5.1%), and above all

more realistic.

5.7

Stability

Driving large capacitive Cload

Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in

the step response.

Figure 37 shows the serial resistor that must be added to the output to make the system stable for a given

capacitive load. The criteria chosen to ensure the stability of the system is an overshoot lower than 30% and with

a settling time at 2.5% of the final value lower than 20 µs.

Figure 37. Stability criteria with a serial resistor at VCC = 5 V

0.1

1

10

0

2

4

6

8

10

12

14

16

18

20

Stable

Vcc=5V, Vicm=12V,

T=25°C

Unstable

Capacitive Load (nF)

5.8

Power supply recommendation

To decouple the TSC20x correctly, it is recommended to place a 100 nF bypass capacitor between Vcc and Gnd.

This capacitor must be placed as close as possible to the supply pins. Figure 38 describes the application setup

for the startup phase. A Vicm = 12 V and a Vsense = 70 mV are set on the input pins of the current sensing. The

current sensing output is directly connected to the comparator input pin.

Figure 39 shows a startup time for current sensing and integrated comparator, with a decoupling capacitance of

100 nF.

TSC200, TSC201, TSC202

Application information

DS13882 - Rev 3

page 19/34