L99PM72PXP datasheet(41/128 Pages) STMICROELECTRONICS

41 / 128 page

L99PM72PXP

Detailed description

Doc ID 023553 Rev 3

41/128

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) is in high impedance state. A low signal activates the output driver and a

serial communication can be started. The state during CSN = 0 is called a communication

frame.

If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not block

the signal line for other SPI nodes.

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI are

sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.

At the rising edge of the CSN signal the contents of the shift register is transferred to Data

Input Register. The writing to the selected Data Input Register is only enabled if exactly 24

bits are transmitted within one communication frame (i.e. CSN low). If more or less clock

pulses are counted within one frame the complete frame is ignored. This safety function is

implemented to avoid an activation of the output stages by a wrong communication frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected IC's is

recommended.

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and goes from high

impedance to a low or high level depending on the global error flag (fault condition). The first

rising edge of the CLK input after a high to low transition of the CSN pin transfers the

content of the selected status register into the data out shift register. Each subsequent

falling edge of the CLK shifts the next bit out.

Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the

falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 1 MHz.

L99PM72PXP Arkusz danych(PDF) 41 Page - STMicroelectronics