BOOT

43.01nc

C

2.2V

=

TOTAL

0.95

Q

43nC

10 A

100kHz

=

+

m

´

Max

TOTAL

gmax

HBO

SW

D

Q

Q

I

F

=

+

´

TOTAL

BOOT

HB

Q

C

V

=

D

LM5102

SNVS268B – MAY 2004 – REVISED DECEMBER 2014

www.ti.com

Typical Application (continued)

8.2.1 Design Requirements

PARAMETERS

VALUES

Gate Drive IC

LM5102

Mosfet

CSD18531Q5A

VDD

10 V

Qgmax

43 nC

Fsw

100 kHz

DMax

95%

IHBO

10 µA

VDH

1.1 V

VHBR

7.1 V

VHBH

0.4 V

8.2.2 Detailed Design Procedure

ΔVHB = VDD – VDH – VHBL

where

•

VDD = Supply voltage of the gate drive IC

•

VDH = Bootstrap diode forward voltage drop

•

Vgsmin = Minimum gate source threshold voltage

(1)

(2)

(3)

The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the mosfet.

(4)

QTOTAL = 43.01 nC

(5)

In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where

the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the

HB Pin voltage above the UVLO Voltage for the HB circuit.

As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.

VHBL = VHBR – VHBH

(6)

VHBL = 6.7 V

(7)

ΔVHB = 10 V – 1.1 V – 6.7 V

(8)

ΔVHB = 2.2 V

(9)

(10)

CBOOT = 19.54 nF

(11)

The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be

twice that of the maximum VDD to allow for loss of capacitance once the devices have a dc bias voltage across

them and to ensure long term reliability of the devices.

The resistor values, RT1 and RT2, for setting turn on delay can be found in Figure 18.

12

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