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SPC563M60L7 Arkusz danych(PDF) 39 Page - STMicroelectronics |
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SPC563M60L7 Arkusz danych(HTML) 39 Page - STMicroelectronics |
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39 / 128 page ![]() DocID14642 Rev 12 39/128 SPC563M64x, SPC563M60x Overview 127 2.4 SPC563Mxx series architecture 2.4.1 Block diagram Figure 1 shows a top-level block diagram of the SPC563Mxx series. Figure 1. SPC563Mxx series block diagram 2.4.2 Block summary Table 3 summarizes the functions of the blocks present on the SPC563Mxx series microcontrollers. PLL Nexus 2+ MMU Nexus SRAM SIU Calibration Interface eDMA Reset Control 62 KB Interrupt External IMUX GPIO & Engine JTAG Nexus RAM 14 KB/3 KB 2x ADCI eTPU Pad Control JTAG Port Nexus Port Analog Vstby e200z335 Interrupt Blocks & eDMA SPE 16 Ch. DSPIs eMIOS Controller 2x CANs 32 Ch.+ AMUX ADC Bus BAM S M M S eQADC NEXUS 1 Peripheral Bridge Peripheral Requests from Interrupt Request Interrupt Request eDMA, FLASH, Bridge B, crossbar, SRAM Configuration eTPU I/O Clocks Serial Analog IF DMA Requests from Peripheral Blocks M Instructions Data S Voltage Regulator (1.2V, 3.3V, STB RAM) NMI SWT PIT critical STM NMI SIU eSCIs 2x . . . . . . . . . . . . (INTC) ADC Decimation Filter CQM Temp. Sensor 1.5 MB Flash S |
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