IS66/67WVS2M8ALL/BLL

Integrated Silicon Solution, Inc.- www.issi.com

11

Rev. A1

11/13/2023

5. READ/WRITE OPERATIONS

5.1 SPI READ OPERATIONS

For all reads, data will be available for tACLK after the falling edge of clock. SPI reads can be done in three

ways:

03h: Serial CMD, Serial IO, slow frequency (1-1-1, 0 Wait Cycle)

0Bh: Serial CMD, Serial IO, fast frequency (1-1-1, 8 Wait Cycles)

EBh: Serial CMD, Quad IO, fast frequency (1-4-4, 6 Wait Cycles)

Figure 5.1 SPI Read, 03h (1-1-1, Max frequency: 33MHz)

CE#

CLK

SI

0

1

0

0

2

3

4

5

6

7

8

9

10

30

0

0

1

1

0

0

24 Bits Address

31

32

33

tACLK

29

34

41

23

22

21

2

0

1

Cmd

SPI Read(03h)

SO

Q7

Q6

Q4

Q2

Q1

Q3

Q5

Data Out 1

Data out 2

High-Z

Q0

Q7

Q6

36

37

38

39

35

40

Note:

1. Data out goes to High-Z after CE# transitions to HIGH (tHZ).

Figure 5.2 SPI Fast Read, 0Bh (1-1-1, Max frequency: 104MHz)

CE#

CLK

SI

0

1

0

0

2

3

4

5

6

7

8

9

10

30

0

1

1

1

0

0

24 Bits Address

31

32

33

tACLK

29

44

23

22

21

2

0

1

Cmd

SPI Fast Read(0Bh)

SO

Q7

Q6

Q4

Q2

Q1

Q3

Q5

Data Out 1

Data out 2

High-Z

Wait Cycles

(8 Clocks)

Q0

Q7

Q6

39

40

41

42

38

43

48

45

46

47

Note:

1. Data out goes to High-Z after CE# transitions to HIGH (tHZ).