L99H92 datasheet(19/77 Pages) STMICROELECTRONICS

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4.1.1

Physical layer

Figure 13. SPI pins description

GADG120920220953SA

4.1.2

Clock and data characteristics

The ST-SPI can be driven by a microcontroller with its SPI peripheral running in the configuration:

•

CPOL = 0

•

CPHA = 0

Figure 14. SPI signal description

GADG120920220954SA

Any communication frame starts with the falling edge of the CSN (Communication Start). CLK has to be low.

The SDI data is then latched at the following rising CLK edges into the internal shift registers.

After Communication Start the SDO leaves 3-state mode and present the MSB of the data shifted out to SDO. At

all following falling CLK edges, data is shifted out through the internal shift registers to SDO.

The communication frame is finished with the rising edge of CSN. If a valid communication took place (for

example, correct number of CLK cycles, access to a valid address, no parity error), the requested operation

according to the operating code will be performed (write or clear operation).

4.1.3

Communication protocol

SDI frame

The device data-in frame consists of 24 bits (OpCode (2 bits) + Address (6 bits) + Data Byte 2 (8 bits) + Data Byte

1 (8 bits)).

L99H92

ST SPI 4.1

DS14069 - Rev 4

page 19/77

L99H92 Arkusz danych(PDF) 19 Page - STMicroelectronics