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ICS853014BGL Arkusz danych(PDF) 9 Page - Integrated Device Technology |
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ICS853014BGL Arkusz danych(HTML) 9 Page - Integrated Device Technology |
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9 / 19 page ![]() ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 9 ICS853014BG REV. DNOVEMBER 12, 2007 Parameter Measurement Information, continued Setup and Hold Time Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2. Single-Ended Signal Driving Differential Input t HOLD t SET-UP PCLKx PCLKx EN Single Ended Clock Input VCC PCLKx nPCLKx R1 C1 0.1u R2 1K 1K V_REF |
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