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HCF4099B Arkusz danych(PDF) 3 Page - STMicroelectronics |
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HCF4099B Arkusz danych(HTML) 3 Page - STMicroelectronics |
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3 / 14 page ![]() LOGIC DIAGRAM Definition of WRITE DIABLE ON Time Mode Selection Types WD R Addressed Latch Unaddressed Latch A 0 0 Follows Data Holds Previous State B 0 1 Follows Data Reset to ”0” (active high 8-channel demultiplexer) C 1 0 Holds Previous State D 1 1 Reset to ”0” Reset to ”0” WD = WRITE DISABLE R = RESET 1 of 8 latches Master Timing Diagram HCC/HCF4099B 3/14 |
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