IMSA110 datasheet(20/26 Pages) STMICROELECTRONICS

20 / 26 page

Enable greater than

BCR1[0]

Default: 0

This control bit determines whether the comparator

in the statistics monitor behaves as a ‘greater than’,

or as a ‘less than’ comparator. The signal from this

comparator is used to drive the Over / Undershoot

Counter and the Max / Min Register. A one at this

location selects ‘greater than’.

BCR1[1-0]

Statistics monitor mode

0 0

Min. register *

0 1

Max. register

1 0

Undershoot counter

1 1

Overshoot counter

10.6 Backend control register 2 (BCR2)

Reserved

BCR2[7]

Default: 0

This location is reserved. The user should write

zero to this location to maintain compatibility with

future products. The value read from this location

will be zero.

Pass LUT data to

least significant

output

BCR2[6]

Default: 0

This bit controls the output multiplexer. If this bit is

set to one, the selected byte from the LUT is output

on the least significant byte (bits 7 to 0) of the

Cascade Output pins.

Pass LUT data to most

significant output

BCR2[5]

Default: 0

This bit controls the output multiplexer. If this bit is

set to one, the selected byte from the LUT is output

on the most significant byte (bits 21 to 14) of the

Cascade Output pins.

Look up prescaler

BCR2[4-0]

Default: 00000

The contents of these five bits control the amount

of (arithmetic) right shift applied to the data, by the

Look up Prescaler. Writing a numerical value be-

tween 0 and 16 (binary 10000) into these bits, will

cause the data to be right-shifted by a correspond-

ing number of places. For example, if the bit pattern

00101 is written to these five bit positions, a right

shift of 5 places will occur. Writing any value outside

the range (0 to 16) will result in undefined behaviour

of the look up Prescaler.

10.7 Backend control register 3 (BCR3)

Normalizer control

BCR3[7-3]

Default: 00000

These five bits control the number of places, that

the normaliser shifts the data to the right or to the

left. This field is interpreted as a twos complement

number. A positive number is taken to be a right

shift. Any shift in the range -2 (11110) to +14 (01110)

is legal. Any other value will cause the number zero

to be output from the normaliser.

Enable dynamic

normalization

BCR3[2]

Default: 0

If this bit is set to one, the normaliser will be con-

trolled by bits 26 to 22 from the output of the look

up table, instead of BCR3[7-3].

Feed LUT data to

output adder

BCR3[1]

Default: 0

One of the inputs of the Output Adder can be either

supplied by the Look up Table or forced to zero.

Setting this control bit to zero selects zero. Setting

this control bit to one selects bits 21 to 0 of the Look

up Table.

Reserved

BCR3[0]

Default: 0

This location is reserved. The user should write

zero to this location to maintain compatibility with

future products. The value read from this location

will be zero.

IMSA110

20/26

IMSA110 Arkusz danych(PDF) 20 Page - STMicroelectronics

IMSA110 Arkusz danych(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Arkusz danych Pobierz

Link URL