3 of 12
RF5117C
Rev A6 DS071018
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Pin
Function
Description
Interface Schematic
1RF IN
RF input. Matching network with DC block required, see evaluation board
schematic for details.
2BIAS GND1
Ground for first stage bias circuit. Not connected.
See pin 5.
3PWR SEN
The PWR SEN and PWR REF pins can be used in conjunction with an exter-
nal feedback path to provide an RF power control function for the
RF5117C. The power control function is based on sampling the RF drive to
the final stage of the RF5117C.
4PWR REF
Same as pin 3.
See pin 3.
5VREG1
This pin requires a regulated supply to maintain nominal bias current.
6VREG2
Same as pin 5.
See pin 5.
7BIAS GND2
Ground for second stage bias circuit. For best performance connect to
ground with a 10nH inductor.
See pin 5.
8NC
Not connected.
9NC
Not connected.
10
RF OUT
RF output and bias for the output stage. The power supply for the output
transistor needs to be supplied to this pin. This can be done through a
quarter-wave length microstrip line that is RF grounded at the other end, or
through an RF inductor that supports the required DC currents.
11
RF OUT
Same as pin 10.
See pin 10.
12
RF OUT
Same as pin 10.
See pin 10.
13
VCC
Interstage match and bias for first stage output. Connect interstage match-
ing capacitor to this pad with a short trace. Connect low-frequency bypass
capacitors to this pin with a long trace. See evaluation board layout for
details.
See pin 1.
14
VCC
Same as pin 13.
See pin 1.
15
NC
Not connected.
16
NC
Not connected.
Pkg
Base
GND
Ground connection. The backside of the package should be connected to
the ground plane through a short path, i.e., vias under the device will be
required.
RF IN
VCC
Bond Wire
Inductance
BIAS
RF OUT
PWR SEN
PWR REF
BIAS
BIAS
VREG1
VREG2
BIAS
GND1
BIAS
GND2
RF OUT
BIAS
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