CY28323PVC datasheet(10/21 Pages) SPECTRALINEAR

10 / 21 page

CY28323PVC

Rev 1.0, November 24, 2006

Page 10 of 21

Data Byte 10

Bit

Pin#

Name

Pin Description

Power On

Default

Bit 7

CPU_Skew2

CPU skew control

000 = Normal

001 = –150 ps

010 = –300 ps

011 = –450 ps

100 = +150 ps

101 = +300 ps

110 = +450 ps

111 = +600 ps

Bit 6

CPU_Skew1

Bit 5

CPU_Skew0

Bit 4

Reserved

Bit 3

PCI_Skew1

PCI skew control

00 = Normal

01 = –500 ps

10 = Reserved

11 = +500 ps

Bit 2

PCI_Skew0

Bit 1

3V66_Skew1

3V66 skew control

00 = Normal

01 = –150 ps

10 = +150 ps

11 = +300 ps

Bit 0

3V66_Skew0

Data Byte 11

Bit

Pin#

Name

Pin Description

Power On

Default

Bit 7

ROCV_FREQ_N7

If ROCV_FREQ_SEL is set, the values programmed in

ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be

use to determine the recovery CPU output frequency when

a Watchdog timer time-out occurs.

The setting of FS_Override bit determines the frequency

ratio for CPU and other output clocks. When the

FS_Override bit is cleared, the same frequency ratio stated

in the Latched FS[4:0] register will be used. When it is set,

the frequency ratio stated in the SEL[4:0] register will be

used.

Bit 6

ROCV_FREQ_N6

Bit 5

ROCV_FREQ_N5

Bit 4

ROCV_FREQ_N4

Bit 3

ROCV_FREQ_N3

Bit 2

ROCV_FREQ_N2

Bit 1

ROCV_FREQ_N1

Bit 0

ROCV_FREQ_N0

Data Byte 12

Bit

Pin#

Name

Pin Description

Power On

Default

Bit 7

ROCV_FREQ_SEL

ROCV_FREQ_SEL determines the source of the recover

frequency when a Watchdog Timer time-out occurs. The

clock generator will automatically switch to the recovery

CPU frequency based on the selection on

ROCV_FREQ_SEL.

0 = From latched FS[4:0]

1 = From the settings of ROCV_FREQ_N[7:0] &

ROCV_FREQ_M[6:0]

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