CY28329

Rev 1.0, November 24, 2006

Page 4 of 16

Serial Data Interface (SMBus)

To enhance the flexibility and function of the clock synthesizer,

a two-signal SMBus interface is provided according to SMBus

specification. Through the Serial Data Interface, various

device functions such as individual clock output buffers, etc.

can be individually enabled or disabled. CY28329 support

both block read and block write operations.

The registers associated with the Serial Data Interface

initializes to its default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface can also be used during system

operation for power management functions.

Data Protocol

The clock driver serial protocol accepts only Block Writes from

the controller. The bytes must be accessed in sequential order

from lowest to highest byte, (most significant bit first) with the

ability to stop after any complete byte has been transferred.

Indexed bytes are not allowed.

A Block write begins with a slave address and a WRITE

condition. The R/W bit is used by the SMBus controller as a

data direction bit. A zero indicates a WRITE condition to the

clock device. The slave receiver address is 11010010 (D2h).

A command code of 0000 0000 (00h) and the byte count bytes

are required for any transfer. After the command code, the

core logic issues a byte count, which describes number of

additional bytes required for the transfer, not including the

command code and byte count bytes. For example, if the host

has 20 data bytes to send, the first byte would be the number

20 (14h), followed by the 20 bytes of data. The byte count byte

is required to be a minimum of 1 byte and a maximum of 32

bytes It may not be 0. Figure 1 shows an example of a block

write.

A transfer is considered valid after the acknowledge bit corre-

sponding to the byte count is read by the controller.

Data Byte Configuration Map

Start

bit

Slave Address

1 1 0 1 0 0 1 0

R/W

0/1

A Command Code

0 0 0 0 0 0 0 0

A Byte Count =

N

A

Data Byte 0

A

. . .

Data Byte N-1

A

Stop

bit

1 bit

7 bits

1

1

8 bits

1

8 bits

1

8 bits

1

8 bits

1

1 bit

Figure 1. An Example of a Block Write

From Master to Slave

From Slave to Master

Data Byte 0: Control Register (0 = Enable, 1 = Disable)

Bit

Affected

Pin#

Name

Description

Type

Power On

Default

Bit 7

5, 6, 7, 10,

11, 12, 13,

16, 17, 18,

33, 35

PCI [0:6]

CPU[3:0]

3V66[1:0]

Spread Spectrum Enable

0 = Spread Off, 1 = Spread On

R/W

0

Bit 6

–

–

Reserved, set = 0

R

0

Bit 5

35

3V66_1/VCH

VCH Select 66 MHz/48 MHz

0 = 66 MHz, 1 = 48 MHz

R/W

0

Bit 4

–

–

Reserved

R

1

Bit 3

10, 11, 12,

13, 16, 17,

18

PCI [6:0]

PCI_STOP#, 0 = stopped, 1 = running

(Does not affect PCI_F [2:0] pins)

R/W

1

Bit 2

40

S2

S2

Reflects the value of the S2 pin sampled on Power-up

RHW

Bit 1

55

S1

S1

Reflects the value of the S1 pin sampled on Power-up

RHW

Bit 0

–

–

Reserved

R

1