Table of Address Values

S0, S1, S2 always 1 - any other value indicates a

packet for use by another chip.

S2 may be used only as part of the VCM register

address, as ATT_EN.

Register

A0-3

R/W

VCM DAC

11xx

Write Only

Aux Control Register

0111

R/W

VCM Control Register

0001

R/W

Commutation Preload

Register (CPR)

0011

Write Only

Test Register (*)

1000

R/W

Status Register

0100

Read only

(*) represents revised specification.The test register is now imple-

mented in both chips

REGISTER BIT DEFINITIONS

All bits in the control registers are asserted (true)

when positive. The appropriate status bit answers

to the same address and bit location as the wri-

table bit which causes the action.

This means that when a read is performed, the

actual value read back is not just an echo from

the write register, but represents the status of the

function requested. In most cases this is a direct,

unlatched output from internal circuitry.

Most status bits are reset after being read once.

The control registers have control bits as follows:

Test conditions for serial port timing spec:

Parameter

From/To

Min.

Max.

Units

SCLK rise, fall

5

ns

2.4

V

0.8

V

2.4

V

Note: The serial port must meet these specifications up to the thermal shutdown temperature.

Figure 7. Serial Port Read Timing Waveforms

Figure 8. Serial Port Write Timing Waveforms

L6256

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