MPC7448 datasheet(28/60 Pages) FREESCALE

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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4

Freescale Semiconductor

Pinout Listings

VDD_SENSE

G13, N12

—

Notes:

1. OVDD supplies power to the processor bus, JTAG, and all control signals, and is configurable. (VDD supplies power to the

processor core, and AVDD supplies power to the PLL after filtering from VDD). To program the I/O voltage, see Table 3. If used,

the pull-down resistor should be less than 250

Ω. Because these settings may change in future products, it is recommended

BVSEL[0:1] be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure

the termination of this signal in the future if necessary. For actual recommended value of Vin or supply voltages see Table 4.

2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OVDD.

3. These pins require weak pull-up resistors (for example, 4.7 K

Ω) to maintain the control signals in the negated state after they

have been actively negated and released by the MPC7448 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull-up resistor to OVDD or negation by ¬HRESET (inverse of HRESET), to

ensure proper operation.

6. Internal pull up on die.

7. Not used in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the MPC7448 is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.

11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were

NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes.

12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.

13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software.

14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.

15.These pins were NCs on the MPC7447, MPC7445, and MPC7441. See Section 9.3, “Connection Recommendations,” for

more information.

16.These pins were OVDD pins on the MPC7447, MPC7445, and MPC7441. These pins are internally connected to OVDD and

are intended to allow an external device (such as a power supply) to detect the I/O voltage level present inside the device

package. If unused, it is recommended they be connected to test points to facilitate system debug; otherwise, they may be

connected directly to OVDD or left unconnected.

17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature

of the processor. These pins may be left unterminated if unused.

18.These pins are internally connected to VDD and are intended to allow an external device (such as a power supply) to detect

the processor core voltage level present inside the device package. If unused, it is recommended they be connected to test

points to facilitate system debug; otherwise, they may be connected directly to VDD or left unconnected.

19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground

voltage level present inside the device package. If unused, it is recommended they be connected to test points to facilitate

system debug; otherwise, they may be connected directly to GND or left unconnected.

20.These pins were in the TEST[0:4] factory test pin group on the MPC7447A, MPC7447, MPC7445, and MPC7441. They have

been assigned new functions on the MPC7448.

21.These pins can be used to enable the supported dynamic frequency switching (DFS) modes via hardware. If both are pulled

down, DFS mode is disabled completely and cannot be enabled via software. If unused, they should be pulled up to OVDD

to allow software control of DFS. See the MPC7450 RISC Microprocessor Family Reference Manual for more information.

22.This pin is provided to allow operation of the L2 cache at low core voltages and is for factory use only. See the MPC7450

RISC Microprocessor Family Reference Manual for more information.

Table 11. Pinout Listing for the MPC7448, 360 HCTE Package (continued)

Signal Name

Pin Number

Active

I/O

Notes

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