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CY2DP314
Document #: 38-07550 Rev.*G
Page 10 of 10
Document History Page
Document Title: CY2DP314 FastEdge
SERIES 1:4 Differential Clock/Data Fanout Buffer
Document Number: 38-07550
REV. ECN NO. Issue Date
Orig. of
Change
Description of Change
**
126779
06/13/03
RGL
New data sheet
*A
128940
08/19/03
RGL
Changed the operation value from 1.5 GHz, reduced swing to 3 GHz to from DC to
above 1.5 GHz
Changed VCC value in the IIN parameter from 3.6V to 3.645V.
Changed the VOL min value from VCC–1.9 to VCC–1.945
Changed the IEE max value from 48 mA to 130 mA
Specified the max input frequency (FCLK) to 2200 MHz
Specified the TTB max value to 250 ps
*B
207710
See ECN
RGL
Added Junction Temperature (TJ) parameter in the Absolute Max. Conditions table
Replaced ICC calculation with power calculation in the footnote
*C
237748
See ECN
RGL
Provided data for TBDs to match the device
*D
247603
See ECN RGL/GGK Changed VOH and VOL to match the Char Data
*E
270151
See ECN
RGL
Removed all VBB references
Added Lead-free devices
*F
346157
See ECN
RGL
Minor Change: corrected the CLK_SEL input type to ECL/PECL
*G
393406
See ECN
RGL
Updated Jitter values, Added typical values
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