L9822EPD datasheet(4/11 Pages) STMICROELECTRONICS

4 / 11 page

ELECTRICAL CHARACTERISTICS (Continued)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

INPUT BUFFER (SI, CE, SCLK and RESET pins)

VT–

Threshold Voltage at

Falling Edge

SCLK only

VCC =5V

± 10%

0.2VCC

0.6

VT+

Threshold Voltage at

Rising Edge

SCLK only

VCC =5V

± 10%

0.7VCC

4.15

Hysteresis Voltage

VT+ –VT–

0.85

2.5

Input Current

VCC = 5.50V, 0 < VI <VCC

–10

+ 10

µA

Input Capacitance

0 < VI <VCC

OUTPUT BUFFER (SO pin)

VSOL

Output LOW Voltage

IO = 1.6mA

0.4

VSOH

Output HIGH Voltage

IO = 0.8mA

VCC

– 1.3V

ISOtl

Output Tristate Leakage

Current

0< VO <VCC, CE Pin Held High,

VCC = 5.25V

–20

µA

CSO

Output Capacitance

0 < VO <VCC

CE Pin Held High

ICC

Quiescent Supply

Current at VCC Pin

All Outputs Progr. ON. IO = 0.5A

per Output Simultaneously

SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram)

fop

Operating Frequency

D.C.

MHz

tlead

Enable Lead Time

250

tlag

Enable Lag Time

250

twSCKH

Clock HIGH Time

200

twSCKL

Clock LOW Time

200

tsu

Data Setup Time

Data Hold Time

tEN

Enable Time

250

tDIS

Disable Time

250

Data Valid Time

100

trSO

Rise Time (SO output)

VCC = 20 to 70% CL = 200pF

tfSO

Fall Time (SO output)

VCC = 70 to 20% CL = 200pF

trSI

Rise Time SPI

Inputs (SCK, SI, CE)

VCC = 20 to 70% CL = 200pF

200

tfSI

Fall Time SPI

Inputs (SCLK, SI, CE)

VCC = 70 to 20% CL = 200pF

200

tho

Output Data Hold Time

µs

L9822E

4/11

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