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STM32F427AI Arkusz danych(PDF) 23 Page - STMicroelectronics |
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STM32F427AI Arkusz danych(HTML) 23 Page - STMicroelectronics |
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23 / 240 page  DS9405 Rev 12 23/240 STM32F427xx STM32F429xx Functional overview 44 Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S ICODE DCODE Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB2 peripherals AHB1 peripherals FMC external MemCtl MS30421V6 CCM data RAM 64-Kbyte APB1 APB2 SRAM3 64 Kbyte LCD-TFT Chrom ART Accelerator (DMA2D) |
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