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CYP15G0401TB Arkusz danych(PDF) 16 Page - Cypress Semiconductor

Numer części CYP15G0401TB
Szczegółowy opis  Quad HOTLink II??Transmitter
PDF  30 Pages
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYP15G0401TB Arkusz danych(HTML) 16 Page - Cypress Semiconductor

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PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 16 of 30
Test Loads and Waveforms
VOLC
Output LOW Voltage
(VCC referenced)
100
Ω differential load
VCC – 1.4
VCC – 0.7
V
150
Ω differential load
VCC – 1.4
VCC – 0.7
V
VODIF
Output Differential Voltage
|(OUT+) – (OUT–)|
100
Ω differential load
450
900
mV
150
Ω differential load
560
1000
mV
Power Supply
Parameter
Description
Test Conditions
Typ.[12]
Max.[13]
Unit
ICC
Power Supply Current
REFCLK = Max.
Commercial
610
770
mA
Industrial
820
mA
ICC
Power Supply Current
REFCLK = 125 MHz
Commercial
590
750
mA
Industrial
800
mA
CYP15G0401TB DC Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
CYP15G0401TB AC Characteristics Over the Operating Range
Parameter
Description
Min.
Max.
Unit
CYP15G0401TB Transmitter LVTTL Switching Characteristics Over the Operating Range
fTS
TXCLKx Clock Frequency
19.5
150
MHz
tTXCLK
TXCLKx Period
6.66
51.28
ns
tTXCLKH
[16]
TXCLKx HIGH Time
2.2
ns
tTXCLKL
[16]
TXCLKx LOW Time
2.2
ns
tTXCLKR
[16, 17, 18]
TXCLKx Rise Time
0.2
1.7
ns
tTXCLKF
[16, 17, 18]
TXCLKx Fall Time
0.2
1.7
ns
tTXDS
Transmit Data Set-Up Time to TXCLKx
↑ (TXCKSEL ≠ LOW)
1.7
ns
tTXDH
Transmit Data Hold Time from TXCLKx
↑ (TXCKSEL ≠ LOW)
0.8
ns
fTOS
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency
20
150
MHz
tTXCLKO
TXCLKO Period
6.66
51.28
ns
Notes:
12. Maximum ICC is measured with VCC = MAX, with all TX channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern to the associated
remote receive channel, and outputs unloaded.
13. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C, with all TX channels enabled and one Serial Line Driver per transmit channel
sending a continuous alternating 01 pattern to the associated remote receive channel. The redundant outputs on each channel are powered down and the
parallel outputs are unloaded.
14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5-pF differential load reflects tester capacitance,
and is recommended at low data rates only.
15. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses the threshold voltage.
16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
17. The ratio of rise time to falling time must not vary by greater than 2:1.
18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
2.0V
0.8V
GND
2.0V
0.8V
RL
3.0V
Vth = 1.4V
[15]
Vth = 1.4V
3.3V
R1
R2
R1 = 590
R2 = 435
(Includes fixture and
probe capacitance)
CL ≤ 7 pF
(a) LVTTL Output Test Load
RL = 100Ω
(b) CML Output Test Load
CL
(c) LVTTL Input Test Waveform
≤ 1 ns
≤ 1 ns
[14]
[14]



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