VL6624 datasheet(17/106 Pages) STMICROELECTRONICS

Numer części	VL6624

Szczegółowy opis	1.3 Megapixel single-chip camera module

PDF	106 Pages

Scroll/Zoom	100%

Producent	STMICROELECTRONICS [STMicroelectronics]

Strona internetowa	http://www.st.com

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VL6624/VS6624

Clock control

17/106

Clock control

Input clock

The VS6624 requires provision of an external reference clock. The external clock should be

a DC coupled square wave. The clock signal may have been RC filtered. The clock input is

fail-safe in power down mode.

The VL6624/VS6624 contains an internal PLL allowing it to produce accurate frame rates

from a wide range of input clock frequencies. The allowable input range is from 6.5MHz to

54MHz. The input clock frequency must be programmed in the registers. To program an

input frequency of 6.5 MHz, the numerator can be set to 13 and the denominator to 2. The

default input frequency is 12 MHz.

The VS6624 may be configured as a master or slave device. In normal (master operation)

the input clock can be a different frequency to the output PCLK and all output clock

configuration is based on the internal PLL. In slave configuration, the input clock is the same

frequency and phase as the output PCLK. i.e. parallel output data is synchronized to the

input clock.

VL6624 Arkusz danych(PDF) 17 Page - STMicroelectronics