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M25P05-AVMP6P Arkusz danych(PDF) 27 Page - Numonyx B.V

Numer części M25P05-AVMP6P
Szczegółowy opis  512 Kbit, serial Flash memory, 50 MHz SPI bus interface
PDF  52 Pages
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Producent  NUMONYX [Numonyx B.V]
Strona internetowa  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25P05-AVMP6P Arkusz danych(HTML) 27 Page - Numonyx B.V

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M25P05-A
Instructions
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6.7
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
There is no address roll-over; when the highest address (0FFFFh) is reached, the
instruction should be terminated.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip
Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read
data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 13.
Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence
1.
Address bits A23 to A16 must be set to 00h.
C
D
AI04006
S
Q
23
2
1
3456789 10
28 29 30 31
22 21
3210
High Impedance
Instruction
24-bit address
0
C
D
S
Q
32 33 34
36 37 38 39 40 41 42 43 44 45 46
765432
0
1
DATA OUT 1
Dummy byte
MSB
7
6543210
DATA OUT 2
MSB
MSB
7
47
765432
0
1
35



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