6.42

7133SA/LA, 7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

14

Jun.16.21

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbitration Controlled by Addresses(1)

NOTES:

1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted

(IDT7133 only).

tAPS(2)

2746 drw 13

ADDR"A" AND "B"

ADDRESSES MATCH

CE"B"

BUSY"B"

tBAC

tBDC

CE"A"

tRC

2746 drw 14

ADDR "A"

ADDRESSES MATCH

ADDR "B"

BUSY "B"

ADDRESSES DO NOT MATCH

tWC

OR

tAPS

tBAA

tBDA

(2)