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M45PE40-VMP6TP Arkusz danych(PDF) 38 Page - Numonyx B.V |
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M45PE40-VMP6TP Arkusz danych(HTML) 38 Page - Numonyx B.V |
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38 / 46 page ![]() DC and AC parameters M45PE40 38/46 Table 14. AC characteristics (50 MHz operation)(1) 50 MHz preliminary data for T9HX technology(2) Test conditions specified in Table 8 and Table 9 Symbol Alt. Parameter Min. Typ. Max. Unit fC fC Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR, RDID D.C. 50 MHz fR Clock frequency for READ instructions D.C. 33 MHz tCH (3) tCLH Clock High time 9 ns tCL (3) tCLL Clock Low time 9 ns Clock slew rate(4) (peak to peak) 0.1 V/ns tSLCH tCSS S active setup time (relative to C) 5 ns tCHSL S not active hold time (relative to C) 5 ns tDVCH tDSU Data in setup time 2 ns tCHDX tDH Data in hold time 5 ns tCHSH S active hold time (relative to C) 5 ns tSHCH S not active setup time (relative to C) 5 ns tSHSL tCSH S deselect time 100 ns tSHQZ (4) tDIS Output disable time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output hold time 0 ns tWHSL Write Protect setup time 50 ns tSHWL Write Protect hold time 100 ns tDP (4) S to Deep Power-down 3 µs tRDP (4) S High to Standby mode 30 µs tRLRH (4) tRST Reset pulse width 10 µs tRHSL tREC Reset recovery time 3 µs tSHRH Chip should have been deselected before Reset is de-asserted 10 ns tPW (5) Page Write cycle time (256 bytes) 11 23 ms tPP (5) Page Program cycle time (256 bytes) 0.8 3ms Page Program cycle time (n bytes) int(n/8) × 0.025 tPE Page Erase cycle time 10 20 ms tSE Sector Erase cycle time 1 5 s 1. Preliminary data. 2. Delivery of parts in T9HX process to start from July 2007. 3. tCH + tCL must be greater than or equal to 1/ fC 4. Value guaranteed by characterization, not 100% tested in production. 5. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2, int(17/8) = 3. |
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