ST7LITEU09 datasheet(66/115 Pages) STMICROELECTRONICS

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10-BIT A/D CONVERTER (ADC) (Cont’d)

11.3.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hard-

ware when software reads the ADCDRH register

or writes to any bit of the ADCCSR register.

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software. It is used

together with the SLOW bit to configure the ADC

clock speed. Refer to the table in the SLOW bit de-

scription.

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bits 4:3 = Reserved. Must be kept cleared.

Bits 2:0 = CH[2:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Note: A write to the ADCCSR register (with ADON

set) aborts the current conversion, resets the EOC

bit and starts a new conversion.

DATA REGISTER HIGH (ADCDRH)

Read Only

Reset Value: 0000 0000 (00h)

Bits 7:0 = D[9:2] MSB of Analog Converted Value

DATA REGISTER LOW (ADCDRL)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:5 = Reserved. Forced by hardware to 0.

Bit 4 = Reserved. Forced by hardware to 0.

Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used

together with the SPEED bit to configure the ADC

clock speed as shown on the table below.

Bit 2 = Reserved. Forced by hardware to 0.

Bits 1:0 = D[1:0] LSB of Analog Converted Value

EOC SPEED ADON

CH2

CH1

CH0

Channel Pin

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

SLOW

fADC

SLOW SPEED

fCPU/2

fCPU

fCPU/4

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