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TDA7500A Arkusz danych(PDF) 25 Page - STMicroelectronics |
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TDA7500A Arkusz danych(HTML) 25 Page - STMicroelectronics |
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25 / 40 page  25/40 TDA7500A EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE Figure 12. External Memory Interface SRAM Read Cycle. Figure 13. External Memory Interface SRAM Write Cycle. Characteristics 40MHz Unit Min. Max. Address Valid and CS Assertion Pulse Width 89 -- ns Address Valid to RD or WR Assertion 23 -- ns RD or WR Assertion Pulse Width 45 -- ns RD or WR Negation to RD or WR Assertion 39 -- ns RD or WR Negation to Address not Valid 5 -- ns Address Valid to Input Data Valid -- 72 ns RD Assertion to Input Data Valid -- 35 ns RD Negation to Data Not Valid (Data Hold Time) 0 -- ns Address Valid to WR Negation 73 -- ns Data Setup Time to WR Negation 32 -- ns Data Hold Time from WR Negation 5 -- ns WR Assertion to Data Valid -- 18 ns WR Negation to Data High-Z (Note 1) -- 23 ns WR Assertion to Data Active 5 -- ns add. [7:0] data add. [13:8] SRA_D [7:0] SRA_D [13:8] ALE DRD add. [7:0] data add. [13:8] SRA [7:0] SRA [13:8] ALE DWR |
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