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M58WR064EB Arkusz danych(PDF) 27 Page - STMicroelectronics |
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M58WR064EB Arkusz danych(HTML) 27 Page - STMicroelectronics |
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27 / 82 page  27/82 M58WR064ET, M58WR064EB Table 9. Configuration Register Bit Description Value Description CR15 Read Select 0 Synchronous Read 1 Asynchronous Read (Default at power-on) CR14 Reserved CR13-CR11 X-Latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 Reserved (default) Other configurations reserved CR10 Wait Polarity 0 WAIT is active Low 1 WAIT is active high (default) CR9 Data Output Configuration 0 Data held for one clock cycle 1 Data held for two clock cycles (default) CR8 Wait Configuration 0 WAIT is active during wait state 1 WAIT is active one data cycle before wait state (default) CR7 Burst Type 0 Interleaved 1 Sequential (default) CR6 Valid Clock Edge 0 Falling Clock edge 1 Rising Clock edge (default) CR5-CR4 Reserved CR3 Wrap Burst 0 Wrap 1 No Wrap (default) CR2-CR0 Burst Length 001 4 words 010 8 words 111 Continuous (CR7 must be set to ‘1’) (default) |
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