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AS1916 - AS1918

Datasheet - Detailed Descr i pti on

8 Detailed Description

The AS1916 - AS1918 supervisory circuits were designed to generate a reset when the monitored supply voltage falls below its factory-trimmed

trip threshold (see VTH on page 4), and to maintain the reset for a minimum timeout period (see tRP on page 4) after the supply has stabilized.

The integrated watchdog timer (see Watchdog Input on page 8) helps mitigate against bad programming code or clock signals, and/or poor

peripheral response.

The active-low manual reset input (see Manual Reset Input on page 8) allows for an externally activated system reset.

8.1 RESET/RESETN

Whenever the monitored supply voltage falls below its reset threshold, the RESET output asserts low or the RESETN output asserts high. Once

the monitored voltage has stabilized, an internal timer keeps the reset asserted for the reset timeout period (tRP). After the tRP period, the

RESET/RESETN output returns to its original state (see Figure 10).

Figure 9. Functional Diagram of VCC Supervisory Application

Figure 10. Reset Timing Diagram

AS1916 - AS1918

Reset Timeout Delay

Generator

Watchdog Transition

Detector

Watchdog

Timer

+

–

VCC

1.26V

2

GND

5

VCC

4

WDI

1

RESETN/

RESET

3

MRN

1V

tRD

tRP

tRP

tRD

VTH

VTH

VCC

RESETN

RESET

GND

1V