R7KA8M2AFDCAM datasheet(218/295 Pages) RENESAS

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RGMII Driver

33 ohms

Input Measurement

point

5pF

Transmission Line

1.00ns delay

50 ohms ±15%

Figure 2.119

RGMII output timing measurement conditions

Table 2.83

ESWM timing (ETn_MDIO, ETn_MDC)

Conditions:

1. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

ESWM

(ETn_MDIO,

ETn_MDC)

ETHn_MDC output cycle

tMDC

2.70 V or

above

—

Figure 2.120

2.30 V or

above

160

—

ETHn_MDIO setup time

(relative to ETHn_MDC↑)

tSMDIO

2.70 V or

above

—

2.30 V or

above

—

ETHn_MDIO hold time

(relative to ETHn_MDC↑)

tHMDIO

2.70 V or

above

—

2.30 V or

above

—

ETHn_MDIO output delay

time (relative to

ETHn_MDC↑)

tDMDIO

2.70 V or

above

2.30 V or

above

tHMDIO

tSMDIO

tDMDIO

tMDC

ETHn_MDIO

(output)

ETHn_MDC

(output)

ETHn_MDIO

(input)

(n = 0, 1)

Figure 2.120

ETn_MDIO, ETn_MDC timing

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 218 of 295

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